1. Field of the Invention
This invention relates to improvement in MOSFET devices, and more particularly to a dual dielectric gate system for use in MOSFET devices, and to methods for making such devices.
2. Description of Related Art Including Information Disclosed under .sctn..sctn.1.97-1.99
A significant yield loss in MOSFET device fabrication is due to particulates during silicon dioxide growth or subsequent metal processing. Thicker dielectrics to reduce these effects tend to accordingly reduce the device transconductance. Moreover, conventional metal or polysilicon gate structures are unforgiving with respect to field stresses, and hence, are ESD sensitive. Conventional silicon dioxide gate systems are sensitive to moisture due to trapping effects.
Gate oxide defects account for one of the largest yield loss mechanisms in MOSFET devices. This failure mechanism is more acute in power VMOS devices where the channel region resides on a plane 54.7.degree. oblique to the planar &lt;100&gt; surface. A thick silicon dioxide gate is imperative to reduce the yield loss due to pin-holes or other defects associated with thin oxides. Unfortunately, this thick gate oxide reduces the device transconductance, a critical device parameter which is proportional to the specific capacitance of the gate oxide. The present polysilicon gate technology employs a thick (typically 5,000 .ANG.) layer of phosphorous doped polysilicon overlaying the thermal silicon dioxide. This heavily doped polysilicon layer serves as the gate electrode of the MOSFET. Although this thick phosphorous doped polysilicon gate helps to protect the underlying gate oxide during subsequent chemical processing, it does not alleviate the problem of gate-to-substrate shorts through the pin-holes or micropores in the thin silicon dioxide. Moreover, the contacting aluminum to the heavily phosphorous doped polysilicon tends to suffer from a galvanic corrosion in the presence of moisture, and thereby, creating a serious reliability failure mechanism.
A dual dielectric gate structure of aluminum/silicon nitride/silicon dioxide has been employed. Although silicon nitride is impervious to alkali ion migration, it suffers from deleterious memory effect (when used for a non-memory device) and has only a slight permitivity advantage over silicon dioxide with a dielectric constant between 5.8 and 6.1. Deposited silicon nitride films have a large amount of built-in tensile stress (approximately 5.times.10.sup.9 dyne/cm.sup.2) when grown at 700.degree. C., as a result, peeling and cracking is a common problem in silicon nitride films.
Stress and strain at the monocrystalline/silicon dioxide interface also has been a problem, because the interface stress and strain influence to a large extent the electronic properties of the silicon dioxide. Thermally grown silicon dioxide normally is in a state of compressive stress. Weaker chemical bond strength at the monocrystalline/silicon dioxide interface results from the difference in stress and strain between the monocrystalline silicon and silicon dioxide. Strain relief has been demonstrated in heavily boron doped silicon epitaxial layers when counterdoped with germanium atoms due to its larger atomic radius compared to boron and silicon by Herzog, "X-Ray Investigation of Boron- and Germanium-Doped Silicon Epitaxial Layers", J. Electrochem. Soc.: SOLID-STATE SCIENCE AND TECHNOLOGY, Dec. 1984, pp. 2969-2974.